Currently, flat panel displays such as liquid crystal display devices or the like have been used for display devices of television sets, personal computers, or the like. The following describes conventional arts of a liquid crystal display device representing flat panel displays as an example. Note that, in the following description, data1, data2, data3 . . . are display data to be respectively written in pixel1, pixel2, pixel3 . . . on a single horizontal line of the liquid crystal display panel in regular display mode, assuming that the pixel1, pixel2, pixel3 . . . are aligned from the left edge to the right edge.
FIG. 11 is a schematic view of an active matrix type liquid crystal display device. As shown in FIG. 11, the liquid crystal display device has a liquid crystal display panel 101, in which a plurality of source bus lines 102 and gate bus lines 103 are provided in a matrix fashion. The source bus lines 102 are connected to a source driver SD, and the gate bus lines 103 are connected to a gate driver GD. The source driver SD is provided along a direction orthogonal to the source bus lines 102 of the liquid crystal display panel 101. The gate driver GD is provided along a direction orthogonal to the gate bus lines 103. The source driver SD and the gate driver GD are operated under control of signals from a controller 106.
At respective intersections of the source bus lines 102 and the gate bus lines 103, TFTs 108 are provided. The source, gate, and drain of each TFT 108 are connected to the source bus line 102, the gate bus line 103, and pixel electrode 109, respectively. The pixel electrodes 109 are connected to opposing electrodes Com through liquid crystal capacities Clc.
In such a liquid crystal display device, using a line-sequential drive, the source driver SD provides data signals to the respective source bus lines 102 simultaneously, and the gate driver GD selects the gate bus lines 103 sequentially. Accordingly, the TFTs 108 connected to the selected gate bus lines 103 (in a selection period) are turned on, so that plural data signals of the source bus lines 102 are written into the pixel electrodes 109 through the TFTs 108. The written data signals are retained until next data signals are written into the pixel electrodes 109, thereby realizing desired display image on the liquid crystal display panel 101.
Next described is a signal transmitting system between the controller 106 and the source drivers SD in the liquid crystal display device.
FIG. 12 illustrates a structure of the liquid crystal display device having a horizontal resolution of 640 dots, for example. That is, there are 640 pixels on one horizontal line. Note that, the gate driver GD is omitted for simplification in FIG. 12. In the following description, each single pixel includes a total of three (red, green, and blue) picture elements.
As shown in FIG. 12, the actual liquid crystal display device has a plurality of source drivers SD, to which the source bus lines 102 are evenly connected. Here, five source drivers SD101 through SD105 are provided. Each of the source drivers SD101 through SD105 is connected to a bundle of 384 source bus lines 102.
The controller 106 sends not only a transmission clock and display data (Data), but also a start pulse SP (Start Pulse), a latch strobe LS (Latch Strobe), and a scanning direction signal DIR. The start pulse SP specifies a starting position of display data. The latch strobe LS is used for latching display data at the respective source drivers SD101 through SD105 simultaneously. The scanning direction signal DIR specifies a scanning direction of the source drivers SD101 through SD105.
The source drivers SD101 through SD105 send display data to the source bus lines 102, through internal flip flop circuits. Such driving circuits are disclosed in Japanese Laid-Open Patent Publication No. 35201/1993 (Tokukaihei 5-35201, publication date: Feb. 21, 1993), for example. Further, the transmission clock is used for setting timings for operating the flip flop circuits, and its frequency is increased in a case of high-definition display. Regarding this, the source drivers SD described later are the same.
Among the signals, only the start pulse SP is sent to a single source driver SD exclusively, while the other signals are commonly sent to all the source drivers SD101 to SD105 via connected buses. That is, a start pulse SP is sent from the controller 106 to a source driver SD provided at an edge of the liquid crystal display panel 101. Then, the start pulse SP is sent from the respective source drivers SD to their following source drivers SD sequentially. Afterwards, a source driver SD provided at another edge of the liquid crystal display panel 101 sends a start pulse SP to the controller 106.
The start pulses SP are supplied as above, due to the following reasons. That is, although sets of display data are commonly sent to all the source drivers SD101 through SD105 via connected buses, the respective source drivers SD101 through SD105 are required to acquire only corresponding display data. Thus, in order to identify display data corresponding to the respective source drivers SD101 through SD105, a start pulse SP is sent as described above.
More specifically, immediately after receiving a start pulse SP (SP1) from the controller 106, the source driver SD 101 acquires required numbers of display data (for first 128 pixels: display data for pixel1 through pixel128) from the display data sent from the controller 106, and then sends a start pulse SP (SP12) for the next source driver SD102. In a similar manner, immediately after receiving the start pulse SP, the source driver SD102 acquires display data for next 128 pixels (display data for pixel129 through pixel256), and then sends a start pulse SP (SP23) to the source driver SD103 of the next stage. In such a manner, the source drivers SD103, SD104, and SD105 acquire display data sequentially. Finally, the controller 106 sends a latch strobe LS for latching data to the respective source drivers SD101 through SD 105, so as to finish sending data of one horizontal line to the source drivers SD101 through SD105. When receiving latch strobes LS, the respective source drivers SD101 through SD105 output voltages corresponding to incoming data to the liquid crystal display panel 101. This operation is repeated for each horizontal line, so that display for one frame is carried out on the liquid crystal display panel 101.
Further, the scanning direction signal DIR, which is sent from the controller 106 commonly to the respective source drivers SD101 through SD105, specifies a shifting direction of the source drivers SD acquiring display data, that is, the scanning direction signal DIR specifies a scanning direction. In the case described above, the scanning direction signal DIR specifies left-to-right scanning (scanning direction from the source drivers SD101 toward SD105: DIR=L). Therefore, the operation of acquiring sets of display data corresponding to the source drivers SD101 through SD105 shifts from the source driver SD101 toward SD105. Further, sets of display data of each horizontal line are sent to the source drivers SD101 through SD105 in accordance with a sequence of data1, data2, . . . , data640, so that regular display having no left-and-right inversion is carried out.
On the contrary, FIG. 13 illustrates a case of carrying out left-and-right inverted display. Unlike regular display, a start pulse SP is first sent from the controller 106 to the source driver SD105. Then, a start pulse SP is sequentially sent from the SD105 to its following source driver SD104, and then from the SD104 to its following SD103. Finally, the source driver SD101 sends a start pulse SP to the controller 106. Further, the scanning direction signal DIR specifies right-to-left scanning (scanning direction from the source driver SD105 toward SD101: DIR=H). Therefore, in a manner opposite to regular display, the operation of acquiring sets of display data corresponding to the source drivers SD101 through SD105 shifts from the source driver 105 toward 101. Further, sets of display data of a single horizontal line are, in a manner similar to regular display, sent to the source drivers SD105 through SD101 in accordance with a sequence of data1, data2, . . . , data640, so that left-and-right inverted display is properly carried out.
As described above, in the conventional liquid crystal display device having a left-and-right inversion function, a start pulse SP can be sent to either one of the source drivers SD101 and SD105 provided at the left and right edges of the liquid crystal display panel 101.
Note that, left-and-right inverted display is used for viewing a reflected image of the liquid crystal display device on a mirror. It is also used for utilizing some visual characteristics of a liquid crystal panel which has different visual characteristics in vertical direction, for example, by reversing its normal settings.
As shown in FIG. 14, a large liquid crystal display device is typically driven in a dual port input by splitting a screen into left and right sections. For example, in a liquid crystal display device having 1280 pixels on a single horizontal line, a screen is split into a left screen having 640 pixels (pixel1 through pixel640) and a right screen having 640 pixels (pixel640 through pixel1280) on a single horizontal line. Each of these two screens is simultaneously driven by a signal prepared for each screen.
More specifically, the liquid crystal display device shown in FIG. 14 has a liquid crystal display panel 111 including a left panel section 111a and a right panel section 111b. The left panel section 111a having source drivers SD111 through SD115 corresponding to the left screen and the right panel section 111b having source drivers SD116 through SD120 corresponding to the right screen.
When such a liquid crystal display device carries out regular display, start pulses SP (SP1 and SP6) are sent to source drivers SD111 and SD116, which are provided at respective left edges of the left panel section 111a and the right panel section 111b. Based on the start pulses SP, the source drivers SD111 and SD116 acquire display data of pixel1 through pixel128 and display data of pixel641 through pixel768, respectively, from data sent from the controller 116. On completion of acquiring the display data, the source drivers SD111 and SD116 send start pulses SP (SP12 and SP67) for the respective source drivers SD112 and SD117. As with the above, subsequent source drivers SD acquire display data, so that sending data of one horizontal line to the source drivers SD111 through SD120 finishes. This operation is repeated for each horizontal line, so that display for one frame is carried out on the liquid crystal display panel 111.
In the above operation, the scanning direction signal DIR, which is sent from the controller 116 commonly to the respective source drivers SD111 through SD120, specifies left-to-right scanning (DIR=L). Further, sets of display data for each horizontal line are sent to the source drivers SD111 through SD115 and SD116 through SD120 in accordance with a sequence of data1, data2, . . . data640, and data641, data642, . . . , data1280, so that regular display having no left-and-right inversion is carried out.
FIG. 15 is a timing chart of the signals for the above operations. In FIG. 15, SP1 is a start pulse SP sent from the controller 116 to the source driver SD111. CKL is a transmission clock, DataL is display data, and LSL is a latch strobe LS, all of which are sent from the controller 116 to the source drivers SD111 through SD115 of the left panel section 111a. In a similar manner, SP6 is a start pulse SP sent from the controller 116 to the source driver SD116. CKR is a transmission clock, DataR is display data, and LSR is a latch strobe LS, all of which are sent from the controller 116 to the source drivers SD116 through SD120 in the right panel section 111b. 
On the contrary, FIG. 16 illustrates a case of carrying out left-and-right inverted display. Unlike regular display, start pulses SP (SP5 and SP10) are first sent from the controller 116 to the source drivers SD115 and SD120 which are provided at respective right edges of the left panel section 111a and the right panel section 111b. Afterwards, the start pulses SP are sequentially sent from the source drivers SD115 and SD120 to their following source drivers SD114 and SD119, respectively. Further, the scanning direction signal DIR specifies right-to-left scanning (DIR=H). Therefore, in a manner opposite to regular display, the operation of acquiring sets of display data corresponding to the source drivers SD111 through SD115 and SD116 through SD120 shifts from the source drivers SD115 and SD120 toward SD111 and SD116. Further, in a manner similar to regular display, sets of display data of each horizontal line are sent to the source drivers SD111 through SD115 and SD116 through SD120, respectively, in accordance with a sequence of data1, data2, . . . , data640 and data 641, data642, . . . , data1280, so that normal left-and-right inverted display is carried out.
FIG. 17 is a timing chart of the signals for the above operation. In FIG. 17, codes of the respective signals indicate as described above.
In a liquid crystal display device shown in FIG. 14, phase relations between transmission clocks and start pulses (SP1 and SP6) are important for transmissions toward the source drivers SD111 and SD116. Also, phase relations between transmission clocks and start pulses (SP5 and SP10) are important for transmissions toward the source drivers SD115 and SD120.
As described above, the transmission clock is sent commonly to the source drivers SD111 through SD115, and the transmission clock is commonly sent to the source drivers SD116 through SD120, both via connected buses. On the other hand, a start pulse SP is first sent to the source drivers SD111 and SD116 (regular display) or the source drivers SD115 and SD120 (left-and-right inverted display). Then, the start pulse SP is passed to their following source drivers sequentially. In such a manner, a condition for sending transmission clocks is different from those of the start pulse. Due to less burdens of transmission channels, the start pulse is transmitted faster than the transmission clocks.
Such a state is described with reference to FIGS. 18 and 19. FIG. 18 illustrates a phase relation between a transmission clock and a start pulse SP (SP1) which are sent to the source driver SD101, when the liquid crystal display device shown in FIG. 12 carries out regular display. This phase relation is equivalent to a phase relation between a transmission clock and a start pulse SP which are sent to the source driver SD116 in regular display mode or to the source driver SD115 in left-and-right inverted display mode in the liquid crystal display device shown in FIG. 14. Also, FIG. 19 illustrates a phase relation in the liquid crystal display device shown in FIG. 12, which is a relation between a transmission clock and a start pulse SP (SP5) which are sent to the source driver SD105 in left-and-right inverted display mode (FIG. 13). The phase relation is equivalent to a phase relation between a transmission clock and a start pulse SP which are sent to the source driver SD111 in regular display mode or to the source driver SD120 in left-and-right inverted display mode (FIG. 16) in the liquid crystal display device shown in FIG. 14.
In a state shown in FIG. 18, the phase relation between a transmission clock and a start pulse SP is appropriate, so that a balance between a Tsetup1 period and a Thold1 period in flip flop circuits forming the source drivers SD is properly maintained. On the other hand, in a state shown in FIG. 19, the phase relation between a transmission clock and a start pulse SP becomes imbalanced. A balance between a Tsetup5 period and a Thold5 period is not maintained having a shorter Thold5 period, because a start pulse SP is transmitted earlier than a transmission clock. Note that, the Tsetup and the Thold indicate conditions of timings when the flip flop circuits acquire data. The operation will not be ensured without securing predetermined periods, respectively.
FIG. 12 illustrates the liquid crystal display device with no two-split drive. In order to obtain a left-and-right inversion function, the liquid crystal display device shown in FIG. 12 requires an appropriate phase difference between transmission clocks and start pulses SP in both of the source drivers SD101 and SD105. Further, the liquid crystal display device with a two-split drive shown in FIG. 14 requires an appropriate phase difference between transmission clocks and start pulses SP in both of the source drivers SD111 and SD116, even when left-and-right inversion function is not used (i.e. in regular display mode). That is, the larger the phase difference is, the smaller margins of timing between sending transmission clocks and start pulses SP become in the liquid crystal display device.
On the other hand, FIG. 19 illustrates retardation from the appropriate state shown in FIG. 18. The phase retardation increases as the transmission length of a signal increases. As a result, it becomes hard to adjust timings, thereby restricting a transmission frequency. This problem is prominent in larger liquid crystal display devices having a long distance for transmitting signals, or in liquid crystal display devices carrying out high-definition display at a high transmission frequency.
More specifically, the following occurs in the liquid crystal display device with a two-split drive shown in FIG. 14. In regular display mode, since a transmission distance is shortest to the source driver SD116 and longest to the source driver SD111, it is hard to adjust timings between a transmission clock and a start pulse SP in the source driver SD111. Also, in left-and-right inverted display mode, since a transmission distance is shortest to the SD115 and longest to the SD120, it is hard to adjust timings between a transmission clock and a start pulse SP in the source driver SD120. In this way, the liquid crystal display device with a two-split drive shown in FIG. 14 has difficulties in adjusting timings for sending transmission clocks and start pulses, because start pulses are first sent from the controller 116 to the closest source driver SD and the farthest source driver SD.
Note that, Japanese Laid-Open Patent Publication No. 35221/1993 Tokukaihei 5-35221 (publication date: Feb. 12, 1993) discloses a structure of a dot-sequential drive, and a technique for preventing vertical stripes from appearing in adjacent display regions when carrying out a two-split drive for a display screen. According to the structure described in this publication, the operation of acquiring data signals shifts from driving circuits provided at both ends toward driving circuits in a center region, sequentially. However, this publication describes neither start pulses SP nor the problem due to retardation of start pulses, which serves no solution for the problem.